Logo Lab-STICCFrom sensors to knowledge: Communicate and decide


Team seminars are given by ARCAD members and visiting collaborators (students and researchers), they are open to all pole and lab members.

Usual format: 30 et 40 minutes presentation followed by 15 to 20 minutes for questions and discussion.




  • Introduction to Masking Protection for Symmetric Encryption
    By Fabrice Lozachmeur, Thales, Lab-STICC.
    Lundi 23, Mai 2022, 15h30 (talk & questions 1h30), Amphi Science 1 (Lorient) et visio-conférence (lien transmis par mail avant la présentation via les mailing lists du pôle SHARP et de l'axe transverse Cyber. Contacter Fabrice Lozachmeur si vous n'êtes pas membre d'une de ces listes)
    Slides : https://hal.archives-ouvertes.fr/hal-03676311

    Software and hardware implementations leak information that depends on the manipulated data and operations. Side-channel analysis exploits some correlations between a measured physical value (e.g., computation time, power consumption, electromagnetic radiation) and secret values manipulated inside secure applications. We will first introduce basic attacks based on side-channel observation of the power consumption of codes running on an embedded processor. As a simple target example, we will introduce a widely used symmetric cryptosystem. To protect software and/or hardware systems against such physical attacks, the masking countermeasure is commonly used. It consists in a kind of randomization of critical data such as secrets used in cryptographic algorithms and security functions in operating systems. Masking is popular since it allows mathematical security proofs in specific models. Pure software implementation of masking is possible but is costly. My PhD thesis deals with hardware/software implementations of such protections based on extensions of the instruction set of a RISC-V processor. This presentation will introduce the state of the art and a few technical elements for people without any background in the domain. Slides will be in English and the presentation in French.

  • Ultra-low Power Computing with CGRAs: an architecture, compilation, and application triptych
    By Kévin MARTIN.
    Lundi 21, février 2022, 9h30, visio-conférence,

    Coarse-grained reconfigurable architectures (CGRAs) are ideal computing devices as they provide both flexibility and performance. In this talk, we present a three-part approach that addresses architecture, compilation, and application to reach ultra-low power computing with CGRAs. First, we present a general-purpose Integrated Programmable-Array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state of the art approaches. We then present modifications applied at the application level to support transprecision computing, a variable size floating-point computing to adjust the precision of the results to the application needs. Finally, we present the SIMD and transprecision support in the CGRA. This global approach reaches an average of 10x energy improvement compared to a RISC-V based ultra-low power digital signal processor.




  • FPGAs et calcul dans les groupes finis
    By Yannick Saouter, CNRS, Lab-STICC,  équipe Codes.
    Mardi 22, juin 2021, 14h, visio-conférence, PDFFPGA calcul groupes finis (Yannick Saouter juin 2021)

    Après une introduction du contexte des groupes finis, cet exposé décrit d'abord les techniques de calcul dans les groupes de permutations et et les groupes de matrices. Une deuxième partie présente certaines
    contributions et perspectives des FPGAs pour l'accélération de calcul dans le domaine mathématique. Pour finir, quelques applications dans le domaine des groupes finis sont présentées plus en détails.


  • Subutai: Distributed synchronization primitives for legacy and novel parallel applications
    By Rodrigo Cadore CATALDO
    Monday, October 19, 2020, 14h

    Parallel applications are essential for efficiently using the computational power of a MultiProcessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. The existing solutions either restrict the application to a subset of synchronization primitives, require refactoring the source code of it, or both.
    We introduce Subutai, a hardware/software architecture designed to distribute the synchronization mechanisms over the Network-on-Chip. Subutai is comprised of novel hardware specialized in accelerating synchronization operations, a small private memory for recording events, an operating system driver, and a user space custom library that supports legacy and novel parallel applications.
    We target the POSIX Threads (PThreads) library as it is widely used as a synchronization library, and internally by other libraries such as OpenMP and Threading Building Blocks. We also provide extensions to Subutai intended to further accelerate parallel applications in two scenarios: (i) multiple applications running in a highly-contended scheduling scenario; (ii) remove the access serialization to condition variables in PThreads. Experimental results with four applications from the PARSEC benchmark running on a 64-core MPSoC show an average application speedup of 1.57× compared with the legacy software solutions. The same applications are further sped up to 5% using our proposed Critical Section-aware scheduling policy compared to a baseline Round-Robin scheduler without any changes in the application source code.
    Thesis online

  • Réseaux de permutations pour les codes correcteurs : modèles et architectures
    Cyrille Chavet
    Tuesday, February 25, 2020, 14h.

    Avec la fin du projet FlexDEC-5G, projet orienté autour d'architectures flexibles pour la 5G notamment, je souhaite profiter de cette occasion pour retracer les travaux que nous avons menés depuis mon arrivé au sein du Lab-STICC. Ce séminaire proposera une présentation simplifiée de la problématique étudiée et de l'état de l'art, avant d'explorer les différents travaux menés ces dernières années. Ce séminaire se conclura sur l'impact des dernières évolutions des codes correcteurs (3GPP-LTE et 5G) sur la problématique.


  • Implantation d'algorithmes à l'aide de circuits analogiques
    Cyril LAHUEC
    Friday, December 13, 2019, 10h30

  • Introduction to Post Quantum Cryptography
    Timo Zijlstra
    Thursday, July 4, 2019

    Cryptographic key exchange protocols make use of the computational difficulty of certain mathematical problems. The protocols are designed in such a way that finding a fast algorithm to break the cryptosystems would be equivalent to a mathematical breakthrough. RSA for instance, relies on the assumption that there is no polynomial time algorithm to solve the large integer factorization problem. Shor's quantum algorithm shows that this assumption is false. RSA and other cryptographic standards such as ECC, can effectively be broken using a quantum computer. It is therefore important to develop new cryptographic algorithms that are safe in a quantum world. In 2016, the NIST launched a project to select and standardize post quantum cryptographic algorithms. In this talk we will discuss the threat that quantum computing poses to security and introduce some of the proposed solutions.
    Thesis online
  • Energy efficient application mapping onto CGRAs
    Satyajit Das
    Monday, April 29, 2019

    Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as a low power computing alternative providing a high grade of acceleration. However, the area and energy efficiency of these devices are bottlenecked by the configuration/context memory when they are made autonomous and loosely coupled with CPUs. The size of these context memories is of prime importance due to their high area and impact on power consumption. For instance, a 64-word context memory typically represents 40% of a processing element area. In this context, since traditional mapping approaches do not take the size of the context memory into account, CGRAs often become oversized which strongly degrade their performance and interest. In this work, we proposed a context memory aware mapping for CGRAs to achieve better area and energy efficiency. In my talk, I will describe the proposed mapping approach which tries to find at least one mapping solution for a given set of constraints defined by the context memories of the PEs. Another important aspect of application mapping is addressed in this work, which is to support floating point applications onto CGRAs. With the recent advancements in algorithms and performance requirements of applications, supporting only integer and logical arithmetic limits the interest of classical/traditional CGRAs. In this work, we proposed a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration. In my talk, I will also speak about the proposed architecture and compilation flow supporting floating point operations onto CGRAs.


  • Introduction to Elliptic Curve Cryptography
    Arnaud Tisserand (DR CNRS)
    Friday 5 October 2018 - 10h15

    Asymmetric cryptography is a key element in secure systems. Key exchange, digital signature and specific cyphering protocols are mandatory in some secure applications (e.g. embedded systems, WSNs, IoT, internet applications). Elliptic Curve Crypto (ECC) is the current standard for asymmetric crypto in most of countries. We will present what are the basic notions in ECC, what types of computations are performed, examples of crypto protocols, some implementation aspects and protections against physical attacks. This seminar does not assume specific mathematical background.

  • Integrated Programmable-Array accelerator to design heterogeneous ultra-low power manycore architectures
    Rohit Prasad
    6 mars 2018

  • Du prototypage à l’exploitation d’overlays FPGA
    Theotime Bollengier  (thèse soutenue le 15 janvier 2018 sous la direction de Loic Lagadec et Jean-Christophe Le Lann)
    6 mars 2018

    De par leur capacité de reconfiguration et les performances qu’ils offrent, les FPGAs sont de bons candidats pour accélérer des applications dans le Cloud. Cependant, les FPGAs présentent certaines caractéristiques qui font obstacle à leur utilisation dans le Cloud et leur adoption par les clients : premièrement, la programmation des FPGAs se fait à bas niveau et demande une certaine expertise, que n’ont pas nécessairement les clients habituels du Cloud. Deuxièmement, les FPGAs ne présentent pas de mécanismes natifs permettant leur intégration dans le modèle de gestion dynamique d’une infrastructure Cloud.
    Dans ce travail, nous proposons d’utiliser des architectures overlay afin de faciliter l’adoption, l’intégration et l’exploitation de FPGAs dans le Cloud. Les overlays sont des architectures reconfigurables elles-mêmes implémentée sur FPGA. En tant que couche d’abstraction matérielle placée entre le FPGA et les applications, les overlays permettent de monter le niveau d’abstraction du modèle d’exécution présenté aux applications et aux utilisateurs, ainsi que d’implémenter des mécanismes facilitant leur intégration est leur exploitation dans une infrastructure Cloud.
    Ce travail présente une approche verticale adressant tous les aspects de la mise en œuvre d’overlays dans le Cloud en tant qu’accélérateurs reconfigurables par les clients : de la conception et l’implémentation des overlays, leur intégration sur des plateformes FPGA commerciales, la mise en place de leurs mécanismes d’exploitation, jusqu’à la réalisation de leurs outils de programmation. L’environnement réalisé est complet, modulaire et extensible, il repose en partie sur différents outils existants, et démontre la faisabilité de notre approche.