Logo Lab-STICCFrom sensors to knowledge: Communicate and decide


Team seminars are given by ARCAD members and visiting collaborators (students and researchers), they are open to all pole and lab members.

Usual format: 30 et 40 minutes presentation followed by 15 to 20 minutes for questions and discussion.




      • Hardware Security Solutions for Multi-Tenant FPGAs
        By Russel Tessier, University of Massachusetts
        Lundi 4, décembre 2023, 14h00 , CR-204 (Lorient) et visio-conférence

        The increased use of FPGAs in cloud and embedded computing environments has led to a number of potential security risks. The sizable amount of logic resources in these devices makes them amenable to sharing across multiple untrusted tenants. However, the co-location of multiple independent circuits presents the possibility of side-channel and fault injection attacks. In this talk, a series of multi-tenant FPGA attack remediations will be described. These solutions have been performed on multiple families of Intel FPGAs, including state-of-the-art Stratix 10 devices. A sensor-based remediation approach that can prevent a voltage attack within 20 microseconds in a Stratix 10 device will be presented along with a fault remediation technique using partial FPGA reconfiguration. Finally, a recovery approach that allows for fault-free computation rollback for an RSA encryption circuit is described.

      • ARCAD day
        By ARCAD team members.
        Jeudi 30, Novembre 2023, Concarneau

        Presentation by Camille Monière : Toward efficient implementations of IoT communication systems, and beyond
        Presentation by Satyajit DAS : Five Years of Mapping DNNs onto Accelerators
        Presentation by Pascal Cotret : A JIT Code Binary Generator for Hardware Testing
        Presentation by William Pensec : Building Fault Injection Scenarios with Ease

      • Embedded cyber-security: from requirements to technological solutions
        By Sylvain Guilley, CTO & Co-Founder Secure-IC.
        Mercredi 5, Juillet 2023, 09h00 , Amphi Science 2 (Lorient) et visio-conférence
        Slides : https://master-cyberus.eu/mediacenter/uploads/23_cyberus-summer-school_slides_sylvain-guilley.pdf

        Cyber-security has become ubiquitous, from IoT end points to datacenters. In such open and broad ecosystem, the protection of data is a major concern; Indeed, some business activities are at risk. In this regard, "certification" aims at controlling and reducing the extent of cyber-physical attacks. Fortunately, many technological solutions can be leveraged to mitigate all identified threats. In this talk, I'll show how the embedded cyber-security industry is working to map requirements into viable protection technologies, in order to reach the expected level of security.

      • Speculative Loop Pipelining for HLS and its application to RISC-V processor synthesis
        By Steven Derrien, IRISA/INRIA.
        Mercredi 12, Avril 2023, 10h30 , CR-204 (Lorient) et visio-conférence

        Custom hardware accelerators usage is shifting toward new application domains such as graph analytics and unstructured text analysis. These applications expose complex control-flow which is challenging to map to hardware, especially when operating from a C/C++ description using high-level synthesis toolchains. In particular, Loop pipelining (LP) is a key optimization in modern high-level synthesis (HLS) tools for synthesizing efficient hardware datapaths.
        Existing techniques for automatic LP are limited by static analysis that cannot precisely analyze loops with data-dependent control flow and/or memory accesses. We propose a technique for speculative LP that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source level, allowing a seamless integration to development flows using HLS, and we show that it can be used to automatically infer pipelined RISC-V micro-architectures from a purely behavioral representation (in the form of an Instruction Set Simulator).

      • Architectures de calculs in-memory computing à base de mémoires non volatiles
        By Valentin Egloff .
        Lundi 27, Mars 2023, 11h00 , CR-204 (Lorient) et visio-conférence

        Les architectures d’aujourd’hui sont basées sur le modèle de von Neumann qui place au centre l’exécution des instructions. Ces architectures font face à de fortes limitations dans le contexte du big data. En effet, le mur mémoire est un phénomène lié à l’écart grandissant de performances entre les processeurs et les mémoires depuis les années 80. Pour atténuer cet écart, une hiérarchie de caches a été mise en place mais elle a en contrepartie largement augmentée la consommation énergétique sans être adaptée pour les grands jeux de données modernes. Non seulement ces architectures ont du mal avec une masse de données toujours croissantes à cause de leur haute consommation énergétique et leur faible débit, elles ne peuvent plus uniquement se baser sur les avancées technologiques pour s’améliorer. Ceci appelle à un changement de paradigme vers des architectures data centrées où le traitement de quantités de données massives en parallèle est le principe de base.

      • Architecture de SoC hétérogène sécurisée par conception
        By Raphaële Milan, Laboratoire Hubert Curien.
        Jeudi 23, Février 2023, 14h00 , N104 (ENSTA Bretagne) et visio-conférence

      • Efficient Mapping of DNN Models onto Accelerators
        By Satyajit Das, IIT Palakkad.
        Lundi 23, Janiver 2023, 10h30 , CR-204 (Lorient) et visio-conférence

        Deep Neural Network (DNN) models are currently deployed throughout the entire computing spectrum starting from cloud to edge devices due to the wide availability of Domain Specific Accelerators (DSAs). The input tensors in each layer of DNN models are often partitioned/tiled to get accommodated the limited on-chip memory of accelerators, resulting in redundant data movement between the accelerator and off-chip memory. The off-chip data movement is the most energy-consuming factor of the DNN accelerator (around 200X more than compute). Studies show that efficient tiling schedules (commonly referred to as mapping) for a given accelerator and DNN model reduce the data movement between the accelerator and different levels of the memory hierarchy improving performance. However, finding layer-wise optimum mapping for a target architecture within a given energy and latency envelope is an open problem due to the huge search space in the mappings. In this talk, I will try to unfold the different strategies adopted and our proposal for highly energy-efficient mapping.

      • ARCAD day
        By ARCAD team members.
        Lundi 09, Janiver 2023, Concarneau

        Presentation by Quentin Ducasse : VM pour RISC-V : sécurité du JIT et contre-mesure(s) matérielle(s)
        Presentation by Mohamed EL-BOUAZZATI : Towards Low-Power and Low Data-Rate Software-Defined Radio Baseband with RISC-V Processor for Flexibility and Security
        Presentation by Arnaud Tisserand : Optimizing Polynomial Approximations for Function Evaluation


      • TalTech-LabSTICC Research Collaboration on Hardware Security and Reliability Topics
        By Maksim Jenihhin, Tallinn University of Technology.
        Jeudi 13, Octobre 2022, 10h00 , CR-204 (Lorient) et visio-conférence

        First, an overview of recent research results is presented. These include early-design-phase (RTL) assessment of vulnerabilities to side-channel and fault-injection attacks, assessment of DNN hardware accelerators reliability, on-line analysis of design- and soft errors in RISC-V processors, reliability management of heterogeneous FPGA SoCs based computing systems. The second part of the seminar is an open discussion. Assoc. Prof. Maksim Jenihhin is the head of the “Trustworthy and Efficient Computing Hardware” (TECH) research group at TalTech, Estonia. His visit to LabSTICC is organized in frames of the collaboration in the project PARROT SUITED: “SecUre IoT Edge Device” (2021-2022).

      • Introduction to Masking Protection for Symmetric Encryption
        By Fabrice Lozachmeur, Thales, Lab-STICC.
        Lundi 23, Mai 2022, 15h30 (talk & questions 1h30), Amphi Science 1 (Lorient) et visio-conférence (lien transmis par mail avant la présentation via les mailing lists du pôle SHARP et de l'axe transverse Cyber. Contacter Fabrice Lozachmeur si vous n'êtes pas membre d'une de ces listes)
        Slides : https://hal.archives-ouvertes.fr/hal-03676311

        Software and hardware implementations leak information that depends on the manipulated data and operations. Side-channel analysis exploits some correlations between a measured physical value (e.g., computation time, power consumption, electromagnetic radiation) and secret values manipulated inside secure applications. We will first introduce basic attacks based on side-channel observation of the power consumption of codes running on an embedded processor. As a simple target example, we will introduce a widely used symmetric cryptosystem. To protect software and/or hardware systems against such physical attacks, the masking countermeasure is commonly used. It consists in a kind of randomization of critical data such as secrets used in cryptographic algorithms and security functions in operating systems. Masking is popular since it allows mathematical security proofs in specific models. Pure software implementation of masking is possible but is costly. My PhD thesis deals with hardware/software implementations of such protections based on extensions of the instruction set of a RISC-V processor. This presentation will introduce the state of the art and a few technical elements for people without any background in the domain. Slides will be in English and the presentation in French.

      • Ultra-low Power Computing with CGRAs: an architecture, compilation, and application triptych
        By Kévin MARTIN.
        Lundi 21, février 2022, 9h30, visio-conférence,

        Coarse-grained reconfigurable architectures (CGRAs) are ideal computing devices as they provide both flexibility and performance. In this talk, we present a three-part approach that addresses architecture, compilation, and application to reach ultra-low power computing with CGRAs. First, we present a general-purpose Integrated Programmable-Array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state of the art approaches. We then present modifications applied at the application level to support transprecision computing, a variable size floating-point computing to adjust the precision of the results to the application needs. Finally, we present the SIMD and transprecision support in the CGRA. This global approach reaches an average of 10x energy improvement compared to a RISC-V based ultra-low power digital signal processor.




      • FPGAs et calcul dans les groupes finis
        By Yannick Saouter, CNRS, Lab-STICC,  équipe Codes.
        Mardi 22, juin 2021, 14h, visio-conférence, PDFFPGA calcul groupes finis (Yannick Saouter juin 2021)

        Après une introduction du contexte des groupes finis, cet exposé décrit d'abord les techniques de calcul dans les groupes de permutations et et les groupes de matrices. Une deuxième partie présente certaines
        contributions et perspectives des FPGAs pour l'accélération de calcul dans le domaine mathématique. Pour finir, quelques applications dans le domaine des groupes finis sont présentées plus en détails.


      • Subutai: Distributed synchronization primitives for legacy and novel parallel applications
        By Rodrigo Cadore CATALDO
        Monday, October 19, 2020, 14h

        Parallel applications are essential for efficiently using the computational power of a MultiProcessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. The existing solutions either restrict the application to a subset of synchronization primitives, require refactoring the source code of it, or both.
        We introduce Subutai, a hardware/software architecture designed to distribute the synchronization mechanisms over the Network-on-Chip. Subutai is comprised of novel hardware specialized in accelerating synchronization operations, a small private memory for recording events, an operating system driver, and a user space custom library that supports legacy and novel parallel applications.
        We target the POSIX Threads (PThreads) library as it is widely used as a synchronization library, and internally by other libraries such as OpenMP and Threading Building Blocks. We also provide extensions to Subutai intended to further accelerate parallel applications in two scenarios: (i) multiple applications running in a highly-contended scheduling scenario; (ii) remove the access serialization to condition variables in PThreads. Experimental results with four applications from the PARSEC benchmark running on a 64-core MPSoC show an average application speedup of 1.57× compared with the legacy software solutions. The same applications are further sped up to 5% using our proposed Critical Section-aware scheduling policy compared to a baseline Round-Robin scheduler without any changes in the application source code.
        Thesis online

      • Réseaux de permutations pour les codes correcteurs : modèles et architectures
        Cyrille Chavet
        Tuesday, February 25, 2020, 14h.

        Avec la fin du projet FlexDEC-5G, projet orienté autour d'architectures flexibles pour la 5G notamment, je souhaite profiter de cette occasion pour retracer les travaux que nous avons menés depuis mon arrivé au sein du Lab-STICC. Ce séminaire proposera une présentation simplifiée de la problématique étudiée et de l'état de l'art, avant d'explorer les différents travaux menés ces dernières années. Ce séminaire se conclura sur l'impact des dernières évolutions des codes correcteurs (3GPP-LTE et 5G) sur la problématique.


      • Implantation d'algorithmes à l'aide de circuits analogiques
        Cyril LAHUEC
        Friday, December 13, 2019, 10h30

      • Introduction to Post Quantum Cryptography
        Timo Zijlstra
        Thursday, July 4, 2019

        Cryptographic key exchange protocols make use of the computational difficulty of certain mathematical problems. The protocols are designed in such a way that finding a fast algorithm to break the cryptosystems would be equivalent to a mathematical breakthrough. RSA for instance, relies on the assumption that there is no polynomial time algorithm to solve the large integer factorization problem. Shor's quantum algorithm shows that this assumption is false. RSA and other cryptographic standards such as ECC, can effectively be broken using a quantum computer. It is therefore important to develop new cryptographic algorithms that are safe in a quantum world. In 2016, the NIST launched a project to select and standardize post quantum cryptographic algorithms. In this talk we will discuss the threat that quantum computing poses to security and introduce some of the proposed solutions.
        Thesis online
      • Energy efficient application mapping onto CGRAs
        Satyajit Das
        Monday, April 29, 2019

        Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as a low power computing alternative providing a high grade of acceleration. However, the area and energy efficiency of these devices are bottlenecked by the configuration/context memory when they are made autonomous and loosely coupled with CPUs. The size of these context memories is of prime importance due to their high area and impact on power consumption. For instance, a 64-word context memory typically represents 40% of a processing element area. In this context, since traditional mapping approaches do not take the size of the context memory into account, CGRAs often become oversized which strongly degrade their performance and interest. In this work, we proposed a context memory aware mapping for CGRAs to achieve better area and energy efficiency. In my talk, I will describe the proposed mapping approach which tries to find at least one mapping solution for a given set of constraints defined by the context memories of the PEs. Another important aspect of application mapping is addressed in this work, which is to support floating point applications onto CGRAs. With the recent advancements in algorithms and performance requirements of applications, supporting only integer and logical arithmetic limits the interest of classical/traditional CGRAs. In this work, we proposed a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration. In my talk, I will also speak about the proposed architecture and compilation flow supporting floating point operations onto CGRAs.


      • Introduction to Elliptic Curve Cryptography
        Arnaud Tisserand (DR CNRS)
        Friday 5 October 2018 - 10h15

        Asymmetric cryptography is a key element in secure systems. Key exchange, digital signature and specific cyphering protocols are mandatory in some secure applications (e.g. embedded systems, WSNs, IoT, internet applications). Elliptic Curve Crypto (ECC) is the current standard for asymmetric crypto in most of countries. We will present what are the basic notions in ECC, what types of computations are performed, examples of crypto protocols, some implementation aspects and protections against physical attacks. This seminar does not assume specific mathematical background.

      • Integrated Programmable-Array accelerator to design heterogeneous ultra-low power manycore architectures
        Rohit Prasad
        6 mars 2018

      • Du prototypage à l’exploitation d’overlays FPGA
        Theotime Bollengier  (thèse soutenue le 15 janvier 2018 sous la direction de Loic Lagadec et Jean-Christophe Le Lann)
        6 mars 2018

        De par leur capacité de reconfiguration et les performances qu’ils offrent, les FPGAs sont de bons candidats pour accélérer des applications dans le Cloud. Cependant, les FPGAs présentent certaines caractéristiques qui font obstacle à leur utilisation dans le Cloud et leur adoption par les clients : premièrement, la programmation des FPGAs se fait à bas niveau et demande une certaine expertise, que n’ont pas nécessairement les clients habituels du Cloud. Deuxièmement, les FPGAs ne présentent pas de mécanismes natifs permettant leur intégration dans le modèle de gestion dynamique d’une infrastructure Cloud.
        Dans ce travail, nous proposons d’utiliser des architectures overlay afin de faciliter l’adoption, l’intégration et l’exploitation de FPGAs dans le Cloud. Les overlays sont des architectures reconfigurables elles-mêmes implémentée sur FPGA. En tant que couche d’abstraction matérielle placée entre le FPGA et les applications, les overlays permettent de monter le niveau d’abstraction du modèle d’exécution présenté aux applications et aux utilisateurs, ainsi que d’implémenter des mécanismes facilitant leur intégration est leur exploitation dans une infrastructure Cloud.
        Ce travail présente une approche verticale adressant tous les aspects de la mise en œuvre d’overlays dans le Cloud en tant qu’accélérateurs reconfigurables par les clients : de la conception et l’implémentation des overlays, leur intégration sur des plateformes FPGA commerciales, la mise en place de leurs mécanismes d’exploitation, jusqu’à la réalisation de leurs outils de programmation. L’environnement réalisé est complet, modulaire et extensible, il repose en partie sur différents outils existants, et démontre la faisabilité de notre approche.