Conférence : CMOS Invertible logic and its applications

vous êtes chaleureusement conviés à participer à la conférence de Naoya Onizawa qui aura lieu le 10 Novembre - 10:30 Salle : Grand Amphi - IMT-Atlantique.

Veuillez trouver ci-joint le descriptif.

The tile is “CMOS Invertible logic and its applications”.

The abstract is :
Recently, CMOS invertible logic has been presented and is one of the new
computing paradigms based on a probabilistic device model. It is
designed based on stochastic computing that provides bidirectional
operations between inputs and outputs and has been applied for several
critical issues, such as integer factorization and machine learning
(ML). This talk presents an overview of CMOS invertible logic from
principle to application. First, the principle is explained with a
simple design example, and a design flow is introduced, as is an
automatic design tool. Second, the hardware of CMOS invertible logic is
designed using stochastic computing and then evaluated in two
applications implemented on a field-programmable gate array (FPGA) or
application-specific integrated circuits (ASICs). Finally, this talk
ends with related topics and future challenges.

The related papers are:
1) N. Onizawa and T. Hanyu, "CMOS Invertible Logic: Bidirectional
Operation Based on Probabilistic Device Model and Stochastic Computing,"
IEEE Nanotechnology Magazine, vol. 16, issue 1, pp. 33-46, Feb. 2022.
2) D. Shin, N. Onizawa, W. J. Gross , and T. Hanyu,” Training Hardware
for Binarized Convolutional Neural Network Based on CMOS Invertible
Logic,” IEEE Access, vol. 8, pp. 188004-188014, Oct. 2020.
3) N. Onizawa, K. Katsuki, D. Shin, W. J. Gross and T. Hanyu,
"Fast-Converging Simulated Annealing for Ising Models Based on Integral
Stochastic Computing,” IEEE Trans. on Neural Networks and Learning
Systems, (online available)