Time: Friday, 10th of November from 14h to 15h30
Place: IMT Atlantique (Brest campus, room K02-100)
You can also connect with Webex (which runs with any web browser), with the credentials provided at the end.
Organizer: Matthieu Arzel
Abstract: Custom hardware accelerators usage is shifting toward new application domains such as graph analytics and unstructured text analysis. These applications expose complex control-flow which is challenging to map to hardware, especially when operating from a C/C++ description using high-level synthesis toolchains. In particular, Loop pipelining (a variant of the classical software pipelining compiler optimization) is a key optimization in modern high-level synthesis (HLS) tools for synthesizing efficient hardware datapaths. Existing techniques for automatic LP are limited by static analysis that cannot precisely analyze loops with data-dependent control flow and/or memory accesses. We propose a technique for speculative LP that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source level, allowing a seamless integration to development flows using HLS. In particular we show that it can be used to automatically infer pipelined RISC-V micro-architectures from a purely behavioral representation (in the form of an Instruction Set Simulator).
Bio: Steven Derrien is professor at University of Rennes, France, and researcher at IRISA/INRIA. His research interests include compiler techniques for High-Level-Synthesis and FPGA based hardware accelerators.