Logo Lab-STICCFrom sensors to knowledge: Communicate and decide

WG security

Working group on security in hardware and embedded software

The working group (WG) "hardware security" aims to present and discuss contributions as well as technical and bibliographic studies from team members and guests on topics such as: hardware cyber-security, secure circuits, security of embedded software and codes, secure processors, implementation of cryptography, physical attacks, side-channel attacks, fault injection attacks, hardware protections against software attacks, protections, countermeasures, etc.

Default time and location : monday mornings, 09h00 - 10h30, visio-conference.

Announcements are made through a dedicated mailing list (managed by A. Tisserand).


Next Meetings


  • Oct., 2021: ??? 
  • Nov., 2021: ???
  • Dec., 2021: ???


Related seminars and events:


Past Meetings / Archives


Archives for 2021:

  • Sept. 27, 2021:  state of art document(s) presentation by Arnaud T. on the PhD Thesis "Sécurisation systématique d'applications embarquées contre les attaques physiques" by Julien Proy, 2019, TEL-HAL.
  • June 28, 2021: state of art paper(s) presentation by Arnaud T. on "QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks", by D. Jayasinghe, A. Ignjatovic, R. Ragel, J. A. Ambrose and S. Parameswaran. ACM Transactions on Design Automation of Electronic Systems, V. 26, I. 5, June 2021. DOI : 10.1145/3443706
  • May 17, 2021: state of art paper(s) presentation by Philippe T. on "Keystone: An Open Framework for Architecting Trusted Execution Environments", by Dayeol Lee and David Kohlbrenner and Shweta Shinde and Krste Asanovic and Dawn Song. Conference EuroSys'20.
  • Mar. 29, 2021: presentation by Philippe T.: Overview of RISC-V Physical Memory Protection (PMP) and applications
  • Mar. 15, 2021: state of art paper(s) presentation by Cyrille C. : "Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture" By Watson, Neumann, et al.. Technical report n 951, Univ. Cambridge, Oct 2020. PDF and Capability Hardware Enhanced RISC Instructions (CHERI)
    (Dans le cadre des podcasts francophones NoLimitSecu, épisode en avril 2021 sur les projets Morello et CHERI)
  • Mar. 1, 2021: state of art paper(s) presentation by Vianney L.: "Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing." By Jiyong Yu, Lucas Hsiung, Mohamad El'Hajj, and Christopher W. Fletcher. Network and Distributed System Security Symposium (NDSS). 2018. Links: paper, slides, video / GitHub
  • Jan. 25, 2021: state of art paper(s) presentation by Arnaud T.: On Architectural Support for Instruction Set Randomization. G. Christou et al. ACM TACO 2020, DOI: 10.1145/3419841


Archives for 2020:

  • Dec. 14, 2020: state of art paper(s) presentation by Arnaud T.:
    • Countermeasures Against Fault Attacks on Software Implemented {AES}: Effectiveness and Cost by Barenghi, A., Breveglieri, L., Koren, I., Pelosi, G., Regazzoni, F.. Proc. 5th Workshop on Embedded Systems Security (WESS), 2010, DOI: 10.1145/1873548.1873555
    • Software Fault Resistance is Futile: Effective Single-Glitch Attacks by Yuce, B., Ghalaty, N. F., Santapuri, H., Deshpande, C. and Patrick, C. and Schaumont, P.. Proc. 8th International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2016, DOI: 10.1109/FDTC.2016.21
  • Nov. 30, 2020: state of art paper presentation by Vianney L.: "CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity", by Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si Merabet, Michaël Timbert. in proc. of 21st Euromicro Conference on Digital System Design (DSD), 2018. DOI : 10.1109/DSD.2018.00093
  • Nov. 16, 2020: state of paper presentation by Guy G: "Adversarial Attack on Microarchitectural Events based Malware Detectors", by S. M. P. Dinakarrao et al., 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, USA, 2019, pp. 1-6, DOI: 10.1145/3316781.3317762
  • Nov. 2, 2020: contribution presentation by Asim M.:"IE-Cache: Counteracting Eviction-Based Cache Side-Channel Attacks through Indirect Eviction." by Mukhtar M.A., Bhatti M.K., Gogniat G. ICT Systems Security and Privacy Protection. SEC 2020. IFIP Advances in Information and Communication Technology, vol 580. https://doi.org/10.1007/978-3-030-58201-2_3
  • Oct. 19, 2020: state of art paper presentation by Vianney L.:"PHMon: A Programmable Hardware Monitor and Its Security Use Cases" by Leila Delshadtehrani and Sadullah Canakci and Boyou Zhou and Schuyler Eldridge and Ajay Joshi and Manuel Egele, 29th USENIX Security Symposium, 2020. paper, slides, video
  • Sep. 21, 2020: state of art paper presentation by Arnaud T.: "Design Space Exploration for Ultra-Low-Energy and Secure IoT MCU", by Ehsan Aerabi, Milad Bohlouli, Mohammad Hasan Livany, Mahdi Fazeli, Athanasios Papadimitriou, David Hély. ACM TECS May 2020, DOI: 10.1145/3384446
  • Sep. 7, 2020: paper presentation by Guy G.: C. Palmiero, G. Di Guglielmo, L. Lavagno and L. P. Carloni, "Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications," 2018 IEEE High Performance extreme Computing Conference (HPEC), Waltham, MA, 2018, pp. 1-7. DOI: 10.1109/HPEC.2018.8547578
  • July 2, 2020: presentation by Libey D.: Pipelined FPGA coprocessor for Elliptic Curve Cryptography based on Residue Number System. By Pedro Miguens Matutino, Juvenal Araújo, Leonel Sousa and Ricardo Chaves. SAMOS 2017. DOI: 10.1109/SAMOS.2017.8344638
  • March 2, 2020: presentation by Timo Z. of the paper: FPGA Implementation and Comparison of Protections against SCAs for RLWE by T. Zijlstra, K. Bigou, and A. Tisserand. IndoCrypt, Dec. 2019. HAL PDF
  • February 3, 2020: presentation by Rémi F. : "Cryptographie asymétrique et codes correcteurs d'erreurs"
  • January 20, 2020: presentation of internship defense by Noura M. : "Implémentation des opérations sur les courbes elliptiques définies dans des corps finis sur FPGA en utilisant une arithmétique randomisée basée sur le théorème des restes chinois (RNS)"
  • January 6, 2020: presentation of state of art results by Arnaud T. : "protections based redundant on coding at gate level"


Archives for 2019:

  • December 16, 2019: paper presentation by Ghita H.: "Improved side-channel analysis attacks on xilinx bitstream encryption of 5, 6, and 7 series" by MORADI, Amir et SCHNEIDER, Tobias. In International Workshop on Constructive Side-Channel Analysis and Secure Design. Springer, Cham, 2016. p. 71-87.
  • December 2, 2019: paper presentation by Vianney L.: O'Flynn, C., Dewar, A. (2019). On-Device Power Analysis Across Hardware Security Domains. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019(4), 126-153. https://doi.org/10.13154/tches.v2019.i4.126-153
  • November 4, 2019, paper presentation by Arnaud T.: Delledonne, Lorenzo and Zaccaria, Vittorio and Susella, Ruggero and Bertoni, Guido and Melzani, Filippo CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks ACM Transactions on Design Automation of Electronic Systems, Nov. 2018, vol. 23, num. 6, doi: 10.1145/3241047
  • September 23, 2019, paper presentation by Arnaud T.: Giterman, Robert and Keren, Osnat and Fis, Alexander A 7T Security Oriented SRAM Bitcell IEEE TCAS-II, 2019, v. 66, n. 8, doi: 10.1109/TCSII.2018.28861
  • September 9, 2019, faculties only: discussion on Master projects
  • July 1, 2019, paper presentation by Arnaud T.: Barry, Thierno and Courousse, Damien and Robisson, Bruno. Compilation of a Countermeasure Against Instruction-Skip Fault Attacks. Proc. 3rd Workshop on Cryptography and Security in Computing Systems (CS2), 2016. DOI: 10.1145/2858930.2858931, HAL
  • June 17, 2019, presentation by Ghita H.: Hardware implementation of a shuffled AES agaisnt side channel attack
  • May 27, 2019, paper presentation by Chavet C.: SMoTherSpectre: exploiting speculative execution through port contention. By A. Bhattacharyya et al. arxiv 1903.01843v1
  • May 13, 2019, discussion on the WG organization
  • Apr. 29, 2019, paper presentation by Philippe T.: Screaming Channels: When Electromagnetic Side Channels Meet Radio Transceivers. By Giovanni Camurati and Sebastian Poeplau and Marius Muench and Tom Hayes and Auré Francillon. Proceedings of the 25th ACM conference on Computer and communications security (CCS)
  • Mar. 11, 2019, work presentation by Hannah B.: Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment
  • Feb. 11, 2019, paper summarized by Timo Z.: A Masked Ring LWE Implementation, by Oscar Reparaz, Sujoy Sinha Roy, Frederik Vercauteren, and Ingrid Verbauwhede, Proc. Cryptographic Hardware and Embedded Systems (CHES) 2015, pp. 683--702, doi: 10.1007/978-3-662-48324-4_34
  • Jan. 28, 2019, paper summarized by Vianney L.: Krautter, J., Gnad, D., & Tahoori, M. (2018). FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2018(3), 44-68. 10.13154/tches.v2018.i3.44-68
  • 14 Jan. 2019, paper summarized by Arnaud T..: De Mulder, Elke and Eisenbarth, Thomas and Schaumont, Patrick. Identifying and Eliminating Side-Channel Leaks in Programmable Systems. IEEE Design \& Test, Vol. 35, N. 1, pp. 74-89, 2018, DOI: 10.1109/MDAT.2017.2766166


Archives for 2018:

  • 10 Dec. 2018, presentation by Arnab B.: Dynamic Information Flow Tracking Co-processor for ARM
  • 5 Dec. 2018, presentation by Gabriel G.: Hardware arithmetic units and cryptoprocessors for hyperelliptic curve cryptography PhD Defense presentation replay
  • 26 Nov. 2018, presentation by Ghita H.: On comparing side-channel preprocessing techniques for attacking RFID devices, paper presented by Thomas Plos, Michael Hutter and Martin Feldhofer, at the 10th International Workshop on Information Security Applications, Busan, Korea, 2009 DOI: 10.1007/978-3-642-10838-9_13"
  • 29 Oct. 2018, presentation by Arnaud T.: CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management paper presented at the 26th USENIX Security Symposium, 2017 (link to PDF, slides and video)
  • 15 Oct. 2018, presentation by Maria M.: Run-time Detection of Prime+Probe Side-channel Attack on AES Encryption Algorithm paper to be presented at IEEE GIIS-2018, Thessaliniki, Greece (23-25 October)
  • 1 Oct. 2018, summary of RISQ meeting by Timo Z.: PQC standardization process
  • 17 Sep. 2018, presentation by Asim M.: Cache Partitioning to Mitigate Cache Based Side Channel Attacks and Introduction to GEM5
  • 11 June 2018, paper summarized by Cyrille C.: Lu Zhang, Wei Hu, Armaiti Ardeshiricham, Yu Tai, Jeremy Blackstone, Dejun Mu, Ryan Kastner Examining the consequences of high-level synthesis optimizations on power side-channel. 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 1167-1170. IEEEXplore
  • 28 May 2018, paper summarized by Vianney L.: Zelalem Birhanu Aweke, Todd AustinOzone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures. 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2018, pp. 1123-1128. doi: 10.23919/DATE.2018.8342179IEEEXplore
  • 14 May 2018, paper summarized by Ghita H.: DOI:10.1007/978-3-642-55220-5_26, François Durvaux, François-Xavier Standaert and Nicolas Veyrat-Charvillon How to Certify the Leakage of a Chip?. Advances in Cryptology - EUROCRYPT 2014 pp 459-476
  • 23 Apr. 2018, presentation by Timo Z.: some elements on the post-quantum crypto competetion NIST page on Post-Quantum Crypto
  • 09 Apr. 2018, presentation by Arnaud T.: objectives on the leakage evaluation of some FPGA hardwired resources
  • 26 Mar. 2018, presentation by Assim M.: Vulnerabilities in ARM TrustZone Architecture
  • 12 Mar. 2018, presentation by Arnab B.: Securing Multiprocessor NoC
  • 19 Feb. 2018, presentation by Guy G.: HardBlare Labex Project
  • 05 February 2018, paper summarized by Arnaud T.: DSD Conferences, Proceedings DSD 2017, DOI:10.1109/DSD.2017.25, Thomas Hiscock, Olivier Savry and Louis Goubin. Lightweight Software Encryption for Embedded Processors. Proc. Euromicro Conference on Digital System Design (DSD). IEEE. Vienna Austria, Aug. 2017.
  • 22 Jan. 2018, paper summarized by Vianney L.: ASAP conferences Sven Tenzing Choden Konigsmark, Deming Chen, and Martin Wong. High-Level Synthesis for Side-Channel Defense. Proc. IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2017


Archives for 2017:

  • 18 Dec. 2017, presentation by Ghita H.: High level synthesis and security
  • 20 Nov. 2017, papers summarized by Arnaud T.:
    • DDECS conferences, DDECS 2017, DOI: 10.1109/DDECS.2017.7934578, A. Mkhinini and P. Maistri and R. Leveugle and R. Tourki HLS Design of a Hardware Accelerator for Homomorphic Encryption. Proc. 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE. Dresden, Germany. Apr. 2017.
    • IDT 2016, DOI:10.1109/IDT.2016.7843028, PDF A. Mkhinini and P. Maistri and R. Leveugle and R. Tourki and M. Machhout A Flexible {RNS}-based Large Polynomial Multiplier for Fully Homomorphic Encryption. Proc. 11th International Design & Test Symposium (IDT). IEEE. pp. 131-136. Hammamet, Tunisia, Dec. 2016.
  • 06 November 2017: intro to RNS for PKC by Arnaud T.
  • 23 October 2017: intro to LWE for PQC by Timo Z.
  • 16 October 2017, paper summarized by Ghita H.: DAC Conferences, BAYRAK, Ali Galip and REGAZZONI, Francesco and BRISK, Philip, et al. A first step towards automatic application of power analysis countermeasures". Proc. 48th Design Automation Conference DAC. ACM, 2011. p. 230-235.
  • 09 October 2017, paper summarized by Arnaud T.: ReConFig Conferences, Proceedings ReConFig 2015, DOI:10.1109/ReConFig.2015.7393335, C. Jayet-Griffon, M.-A. Cornelie, P. Maistri, Ph. Elbaz-Vincent, and R. Leveugle. Polynomial Multiplication for Homomorphic Encryption on FPGAs. Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexico City, Mexico, Dec. 2015
  • 18 September 2017, presentation by Vincent Migliore (PhD defense preparation) at 8h00
  • 11 September 2017, paper summarized by Guy G.: DATE 2017, DATE conferences, DOI:10.23919/DATE.2017.7927134 Song Bian, Masayuki Hiromoto, and Takashi Satoh SCAM: Secured Content Addressable Memory Based on Homomorphic Encryption. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
  • 26 June 2017, informations on masking countermeasures by Ghita H. CHES 2000, CHES conferences, DOI:10.1007/3-540-44499-8_18, proceedings in PDF cited by GoogleScholar J.-S. Coron and L. Goubin. On Boolean and Arithmetic Masking against Differential Power Analysis. Proc. 2nd International Conference on Cryptographic Hardware and Embedded Systems. LNCS vol. 1965, Worcester, MA, USA. Aug. 2000.
  • 07 June 2017, talk by Gabriel G. from the presentation at: CryptoPuces 2017, HAL (abstract and slides PDF), G. Gallin and A. Tisserand. Hardware Architectures Exploration for Hyper-Elliptic Curve Cryptography. 6ème rencontre CryptoPuces, Porquerolles, France, mai 2017.
  • 29 May 2017, papers summarized by Arnaud T.:
    • FPL 2004, FPL conferences, DOI:10.1007/978-3-540-30117-2_125, PDF Tiri and I. Verbauwhede. Secure Logic Synthesis. Proc. 14th International Conference on Field-Programmable Logic and Applications (FPL). pp. 1052-1056. LNCS vol. 3203 Springer. Antwerp, Belgium. Sep. 2004.
    • PDF from IACR Cryptology ePrint Archives K. Tiri and I. Verbauwhede. Synthesis of Secure FPGA Implementations. Report 68, Feb. 2004.
    • DATE 2004, DATE conferences, PDF, NO DOI K. Tiri and I. Verbauwhede. A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. Proc. Conference on Design, Automation and Test in Europe (DATE). IEEE. Paris, France. Feb. 2004.
  • 22 May 2017, paper summarized by Vianney L.: DOI:10.1109/TVLSI.2016.2530092 J. J. Rajendran, O. Sinanoglu and R. Karri. Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 24, N. 9, pp. 2946-2959, Sep. 2016
  • 18 May 2017, presentation by Cédric S. on Terasic DE5 FPGA card and RIFFA interface tools.
  • 09 May 2017, paper summarized by Vincent M.: SAC 2016, SAC conferences, PDF from IACR Cryptology ePrint Archives, DOI:? J.-C. Bajard, J. Eynard, A. Hasan, V. Zucca. A Full RNS Variant of FV like Somewhat Homomorphic Encryption Schemes. Proc. 23rd International Conference on Selected Areas in Cryptography (SAC), Canada, Aug. 2016
  • 24 April 2017, paper summarized by Maria Mu.: CHES 2016, CHES conferences, DOI:10.1007/978-3-662-53140-2_17, PDF from IACR Cryptology ePrint Archives Yuval Yarom, Daniel Genkin and Nadia Heninger. CacheBleed: A timing attack on OpenSSL constant time RSA. Proc. 18th International Conference on Cryptographic Hardware and Embedded Systems. LNCS vol. 9813, Springer. Santa Barbara, CA, USA. Aug. 2016.
  • 11 April 2017, paper summarized by Arnaud T.: FTDC 2016, FDTC conferences, DOI:10.1109/FDTC.2016.18, PDF from Riscure website N. Timmers, A. Spruyt and M. Witteman. Controlling PC on ARM Using Fault Injection. Proc. 8th International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC). pp. 25-35. IEEE. Santa Barbara, CA, USA. Aug. 2016.