Ph.D. Thesis: Optimized Hardware Designs for Quantum LDPC Decoders
(Partially founded by European QuantERA programme, an international consortium involving partners in France, Germany, Spain and Finland https://quantera.eu/equip/)
Supervisors: Francisco Garcia-Herrero (Universidad Complutense de Madrid - UCM), Emmanuel Boutillon (http://www-labsticc.univ-ubs.fr/~boutillon/anglais.html) (Université Bretagne Sud-UBS)
Funding: UCM (50 %), UBS (50 %), 100k€ + travel and conference expenses.
The last years have seen significant advances in the field of quantum technologies, consolidating the development of basic requirements for quantum computation. Protecting quantum computation from noise and decoherence has become more topical than ever, challenging and bringing quantum error correction (QEC) fairly close to the integration into practical quantum computers. To make such an integration viable, a critical task is to bridge the gap between algorithmic solutions and latency-power-scalability constrained hardware (HW) designs. In fact, the constraints that the quantum technology may impose on the QEC decoder have only recently started to be considered in the literature and may be summarized as follows. Latency: the time budget available to perform a single error correction round varies with the quantum technology, but a first-order approximation is a period of hundreds of nanoseconds (for codes encoding one logical qubit into several thousands of physical qubits, such a time limit corresponds to throughputs in the order of tens of gigabits to terabit/s). Power consumption: there may be a limited power budget, especially for qubit technologies requiring cryogenic cooling, and when the QEC is implemented within the low-temperature layers. Scalability: practical applications will require hundreds of thousands to millions of physical qubits.
Recent references in the topic:
Candidates should have a master’s degree in computer engineering, coding theory, electronics engineering, or a related subject. A proactive approach to algorithmic design, optimization of heavy computational tasks, and digital design are essential. Previous research experience in a relevant area, such as quantum information, FPGA design, or classical coding theory, is desirable but not required.
- Design of iterative message-passing (MP) decoders for quantum LDPC codes: achieve high error correction performance, with hardware-convenient decoding algorithms. Design new decoding rules, and propose simplifications and optimizations of iterative MP decoding algorithms, to provide flexibility between the figures of merit of the HW design.
- Design of scalable NN-based decoding solutions for quantum codes: adapt MP decoding behavior to the QEC protocol, or the noise model. Investigate HW-convenient NN-based decoders, e.g., that can be mapped back to MP decoding algorithms, suitable for later hardware implementations and meeting constraints of the quantum system.
- Develop an FPGA-based prototyping platform, to validate and evaluate the potential implications of our decoding solutions for QEC in large-scale devices, in terms of accuracy, latency, and power constraints.
Application deadline: 9th January 2023
Starting date: End January 2023
How to apply:
Applicants should provide a CV, a motivation letter, and the contact details of at least two references.